Wireless telecommunications and Radio Frequencies (RF) standards call for linear Power Amplifiers (PA) allowing reduced power consumptions. Indeed, new modulated signals with high PAPR (Peak to Average Power Ratio) (6-10 dB) have a huge impact on the Power Amplifier design optimization. As known by a skilled man, such modulations ask for very good linearity and, last but not least, efficiency as well.
To ensure the best performances, circuit designers commonly choose to directly couple the output stage to the battery voltage, when such direct coupling shows to be compatible with the maximum voltage allowed by the particular sub-micron technology being considered. Indeed, generally speaking, sub-micron MOS technology only allows limited voltages and, therefore, raises a reliability issue when higher voltages are to be considered.
One known solution for handling this problem is based on the use, for embodying the RF Power Amplifier, a specific technology which can sustain high voltages at their terminals. For instance, the so-called N lateral Diffused Extended MOS technology offering compatibility with higher voltages may be used for embodying RF output power amplifiers, but at the cost of additional drawbacks, including further non-linearities and higher manufacturing costs.
A conventional power amplifier is known which, at least partly, helps to cope with such problem is the well-known cascode structure which is used for its interesting isolation between the input and the output.
The cascode structure is based on the connection in series of at least two transistors, respectively a common source transistor associated to a common grid transistor), thus allowing to share the high voltage of the battery (at least when fully charged) between two individual transistors. Thanks to such arrangement, only a part (half) of the battery voltage is applied to each individual transistor, thus providing a “partial” protection of the individual cascode components when high voltages are being considered.
However, in wireless communications using battery powered circuits, the level of the battery may vary to a wide extent—typically between 2.5 Volt to 5 Volt and, therefore, the protection which is highly useful when the battery is fully charged becomes inappropriate and might even jeopardize linearity at low values.
In particular, for low voltage values, the PA circuit tends to be less linear and the cascode based PA needs to be combined with complex circuits or feedback loops to re-establish linearity and improve PAE. While the latter feedback loop shows phase issues (resulting in possible instability), the former linearization blocks are area consuming and increase total circuit complexity. Moreover it implies a coupler at the output which at the end reduces overall efficiency.
There is therefore a dilemma to be handled, deriving from the need of a good linearity and the need to allow large voltage swing.
The observations above shows that, so far, there is still a difficulty in reaching a trade off between reliability (maximum voltage sustained on transistor particularly when using a common “basic” sub-micron technology) and performances over a wide range of battery voltage (from 2.7 to 4.8V for instance).
Therefore, there is still a need for a specific RF PA structure allowing direct implementation in pure CMOS technology and which still shows good linearity even with a reduced battery voltage.